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APW7080
4A, 26V, 380kHz, Asynchronous Step-Down Converter
Features
* * * * * * * * * * * * * * *
Wide Input Voltage from 4.5V to 26V Output Current up to 4A Adjustable Output Voltage from 0.8V to 90%VIN - 0.8V Reference Voltage - 2.5% System Accuracy 80m Integrated P-Channel Power MOSFET High Efficiency up to 91% - Pulse-Skipping Mode (PSM) / PWM Mode Operation Current-Mode Operation - Stable with Ceramic Output Capacitors - Fast Transient Response Power-On-Reset Monitoring Fixed 380kHz Switching Frequency in PWM Mode Built-in Digital Soft-Start Output Current-Limit Protection with Frequency Foldback 70% Undervoltage Protection Over-Temperature Protection <5A Quiescent Current during Shutdown Thermal-Enhanced SOP-8P Package Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APW7080 is a 4A, asynchronous, step-down converter with integrated 80m P-channel MOSFET. The device, with current-mode control scheme, can convert 4.5~26V input voltage to the output voltage adjustable from 0.8 to 90% VIN to provide excellent output voltage regulation. The APW7080 regulates the output voltage in automatic PSM/PWM mode operation, depending on the output current, for high efficiency operation over light to full load current.The APW7080 is also equipped with power-onreset, soft-start, and whole protections (undervoltage, over temperature, and current-limit) into a single package. In shutdown mode, the supply current drops below 5A. This device, available in an 8-pin SOP-8P package, provides a very compact system solution with minimal external components and good thermal conductance.
100 90 VOUT =5V VOUT =3.3V
Efficiency (%)
80 70 60 50 40 30 20 10
Simplified Application Circuit
C1 10F VIN VCC C3 UGND LX
U1 APW7080
0.001
0.01
0.1
1
10
+12
VIN
Output Current, IOUT (A)
Applications
* * * * * * *
LCD Monitor / TV Set-Top Box Portable DVD Wireless LAN ADSL, Switch HUB Notebook Computer Step-down Converters Requiring High Efficiency and 4A Output Current
C2 L1 4A
D1 R1 1%
VOUT +3.3V
C4 22F
VIN
EN COMP R4 GND FB R2 1%
C6 C5
C7 (Optional)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2008 1 www.anpec.com.tw
APW7080
Ordering and Marking Information
APW7080 Assembly Material Handling Code Temperature Range Package Code Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXX - Date Code
APW7080 KA :
APW7080 XXXXX
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Pin Configuration
VIN EN UGND VCC
1 2 3 4 8
9 LX
7 6 5
GND FB COMP LX
SOP-8P Top View The Pin 5 must be connected to the Exposed Pad
Absolute Maximum Ratings
Symbol VIN VLX Parameter VIN Supply Voltage (VIN to GND) LX to GND Voltage
(Note 1)
Rating -0.3 ~ 30 > 100ns < 100ns VIN > 6.2V VIN 6.2V -2 ~ VIN+0.3 -5 ~ VIN+6 -0.3 ~ 6.5 < VIN+0.3 -0.3 ~ VIN+0.3 -0.3 ~ 6.5V -0.3 ~ 20 -0.3 ~ VCC +0.3 150 -65 ~ 150 260 Unit V V
VCC VUGND_GND VVIN_UGND
VCC Supply Voltage (VCC to GND) UGND to GND Voltage VIN to UGND Voltage EN to GND Voltage FB, COMP to GND Voltage Maximum Junction Temperature
V V V V V X C X C X C
TSTG TSDR
Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.
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APW7080
Thermal Characteristics
Symbol JA JC Parameter Junction-to-Ambient Resistance in Free Air
(Note 2) o
Typical Value SOP-8P 50 10
Unit C/W C/W
Junction-to-Case Resistance in Free Air (Note 3) SOP-8P
o
Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.
Recommended Operating Conditions
Symbol VIN VOUT IOUT VIN Supply Voltage VCC Supply Voltage Converter Output Voltage Converter Output Current VCC Input Capacitor VIN-to-UGND Input Capacitor TA TJ Ambient Temperature Junction Temperature Parameter
(Note 4)
Range 4.5 ~ 26 4.0 ~ 5.5 0.8 ~ 90% VIN 0~4 0.22 ~ 2.2 0.22 ~ 2.2 -40 ~ 85 -40 ~ 125 Unit V V V A F F
o
C C
o
Note 4: Refer to the typical application circuits
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Symbol SUPPLY CURRENT IVIN IVIN_SD IVCC IVCC_SD VIN Supply Current VIN Shutdown Supply Current VCC Supply Current VCC Shutdown Supply Current VFB = 0.85V, VEN=3V, LX=Open VEN = 0V, VIN=26V VEN = 3V, VCC = 5.0V, VFB=0.85V VEN = 0V, VCC = 5.0V VIN = 5.2 ~ 26V, IO = 0 ~ 8mA IO = 0 ~ 8mA VCC > POR Threshold VIN = 6.2 ~ 26V, IO = 0 ~ 10mA IO = 0 ~ 10mA VIN = 6.2 ~ 26V 1.0 0.7 2.0 5 1 mA A mA A V mV mA Parameter Test Conditions APW7080 Min. Typ. Max. Unit
VCC 4.2V LINEAR REGULATOR Output Voltage Load Regulation Current-Limit VIN-to-UGND 5.5V LINEAR REGULATOR Output Voltage (VVIN-UGND) Load Regulation Current-Limit 5.3 -80 10 5.5 -60 5.7 0 30 V mV mA 4.0 -60 8 4.2 -40 4.5 0 30
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APW7080
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Symbol Parameter Test Conditions APW7080 Min. Typ. Max. Unit
POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS VCC POR Voltage Threshold VCC POR Hysteresis EN Lockout Voltage Threshold EN Lockout Hysteresis VIN-to-UGND Lockout Voltage Threshold VIN-to-UGND Lockout Hysteresis REFERENCE VOLTAGE VREF Reference Voltage TJ = 25oC, IOUT=0A, VIN=12V Output Voltage Accuracy Line Regulation Load Regulation OSCILLATOR AND DUTY FOSC Free Running Frequency Foldback Frequency Maximum Converter' Duty Cycle s Minimum Pulse Width of LX CURRENT-MODE PWM CONVERTER Gm Error Amplifier Transconductance Error Amplifier DC Gain Current-Sense Resistance P-channel Power MOSFET Resistance PROTECTIONS ILIM VUV P-channel Power MOSFET Current-limit FB Under-Voltage Threshold FB Under-Voltage Hysteresis FB Under-Voltage Debounce TOTP Over-Temperature Trip Point Over-Temperature Hysteresis SOFT-START, ENABLE AND INPUT CURRENTS tSS Soft-Start Interval Preceding Delay before Soft-Start EN Shutdown Voltage Threshold EN Enable Voltage Threshold EN Pin Clamped Voltage VEN falling, VIN = 4 ~ 26V VEN rising, VIN = 4 ~ 26V IEN=10mA 9 9 0.5 12 10.8 10.8 12 12 2.1 17 ms ms V V V Peak Current VFB falling 5.0 66 6.5 70 40 2 150 50 8.0 74 A % mV s
o o
VCC rising VEN rising
3.7 2.3 -
3.9 0.15 2.5 0.2 3.5 0.2
4.1 2.7 -
V V V V V V
VVIN-UGND rising
-
-1.0 -2.5 TJ = -40 ~ 125oC, IOUT = 0 ~ 4A, VIN = 4.5 ~ 26V VIN = 4.5V to 26V, IOUT = 0A IOUT = 0 ~ 4A VIN = 4.5 ~ 26V VFB = 0V VIN = 4.5 ~ 26V
0.8 0.36 0.4
+1.0 +2.5 -
V % % %
340 -
380 80 93 200
420 -
kHz kHz % ns A/V dB m
COMP = Open 60 Between VIN and Exposed Pad, TJ=25oC -
400 80 0.12 80
100
C C
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APW7080
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85oC, unless otherwise specified. VCC is regulated by an internal regulator. Typical values are at TA=25oC.
Symbol Parameter Test Conditions APW7080 Min. Typ. Max. Unit
SOFT-START, ENABLE, AND INPUT CURRENTS (Cont.) P-channel Power MOSFET Leakage Current IFB IEN FB Pin Input Current EN Pin Input Current VEN = 0V, VLX = 0V, VIN = 26V VFB = 0.8V VEN < 3V -100 -500 4 +100 +500 A nA nA
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APW7080
Typical Operating Characteristics
Reference Voltage vs. Junction Temperature
0.816
Switching Frequency vs. Junction Temperature
420
Switching Frequency, FOSC (kHz)
-50 -25 0 25 50 75 100
o
0.812
410 400 390 380 370 360 350 340
Reference Voltage, VREF (V)
0.808 0.804 0.800 0.796 0.792 0.788 0.784 125 150
-50
-25
0
25
50
75
100
o
125
150
Junction Temperature, TJ ( C)
Junction Temperature, TJ ( C)
Output Voltage vs. Supply Voltage
3.36 3.35 3.34
I OUT = 1A
Output Voltage vs. Output Current
3.36 3.35 3.34
VIN = 12V
Output Voltage, VOUT (V)
3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 4 6 8 10 12 14 16 18 20 22 24 26
Output Voltage, VOUT (V)
3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Supply Voltage, VIN (V)
Output Current, IOUT (A)
VIN Input Current vs. Supply Voltage
1.6 1.4
VFB =0.85V
Current-Limit Level (Peak Current) vs. Junction Temperature
8.0 7.5 7.0
1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 4 8 12 16 20 24 28
Current-Limit Level, ILIM (A)
VIN Input Current, IVIN (mA)
6.5 6.0 5.5 5.0 -50 -25 0 25 50 75 100 125 150
VIN Supply Voltage, VIN (V) Copyright (c) ANPEC Electronics Corp. Rev. A.6 - Jun., 2008 6
Junction Temperature, TJ (oC) www.anpec.com.tw
APW7080
Typical Operating Characteristics (Cont.)
Efficiency vs. Output Current
100 90 80
VOUT =5V VOUT=5V VOUT=3.3V
EN Clamp Voltage vs. EN Input Current
18 16
EN Clamp Voltage, VEN (V)
14 12 10 8 6 4 2 0 1 10 100 1000 10000
TJ =-30oC
Efficiency (%)
70 60 50 40 30 20 10 0.001
TJ =25oC
TJ =100oC
VIN=12v, L=10H (DCR=50m) C1=10F, C4=22F
0.01
0.1
1
10
Output Current, IOUT (A)
EN Input Current, IEN (A)
Operating Waveforms
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H)
Load Transient Response
I OUT = 50mA -> 3A -> 50mA I OUT rise/f all time=10s
Load Transient Response
I OUT = 0.5A -> 3A -> 0.5A I OUT rise/f all time=10s
1
VOUT
1
VOUT
3A
3A
IL1 IL1
2
0A
2
0.5A
Ch1 : VOUT, 200mV/Div, DC, Voltage Offset = 3.3V Ch2 : IL1, 1A/Div, DC Time : 50s/Div
Ch1 : VOUT, 100mV/Div, DC, Voltage Offset = 3.3V Ch2 : IL1, 1A/Div, DC Time : 50s/Div
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APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H)
Power On
I OUT = 3A
Power Off
I OUT = 3A
1
VIN
VIN
1
VOUT
VOUT
2
2
3
IL1
3
IL1
Ch1 : VIN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div
Ch1 : VIN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div
Enable Through EN Pin
I OUT = 3A
Shutdown Through EN Pin
I OUT = 3A
1
VEN
1
VEN
VOUT
VOUT
2
2
3
IL1
3
IL1
Ch1 : VEN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div
Ch1 : VEN, 5V/Div, DC Ch2 : VOUT, 2V/Div, DC Ch3 : IL1, 2A/Div, DC Time : 5ms/Div
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APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H)
Over Current
I OUT = 1 -> 6A
Short Circuit
VOUT is shorted to ground by a short wire
VOUT
1
VOUT
1
I L1
IL1
2
2
Ch1 : VOUT, 1V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 50s/Div
Ch1 : VOUT, 1V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 50ms/Div
Switching Waveform
I OUT = 0.2A 3A
Switching Waveform
I OUT = 3A
VLX
VLX
1
1
IL1 IL1
2
2
Ch1 : VLX, 5V/Div, DC Ch2 : IL1, 1A/Div, DC Time : 1.25s/Div
Ch1 : VLX, 5V/Div, DC Ch2 : IL1, 2A/Div, DC Time : 1.25s/Div
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APW7080
Operating Waveforms (Cont.)
(Refer to the application circuit 1 in the section "Typical Application Circuits", VIN=12V, VOUT=3.3V, L1=10H)
Line Transient Response
VIN = 12V --> 24V --> 24V VIN rise/f all time=20 s
VOUT
1
VIN
24V
2
12V
Ch1 : VOUT, 50mV/Div, DC, Voltage Offset = 3.3V Ch2 : VIN, 5V/Div, DC, Voltage Offset = 12V Time : 50s/Div
Pin Description
PIN 1 NAME VIN FUNCTION Power Input. VIN supplies the power (4.5V to 26V) to the control circuitry, gate driver and step-down converter switch. Connecting a ceramic bypass capacitor and a suitably large capacitor between VIN and GND eliminates switching noise and voltage ripple on the input to the IC. Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the regulator, drive it low to turn it off. Pull up with 100k resistor for automatic startup. Gate driver power ground of the P-channel Power MOSFET. A linear regulator regulates a 5.5V voltage between VIN and UGND to supply power to P-channel MOSFET gate driver. Connect a ceramic capacitor (1F typ.) between VIN and UGND for noise decoupling and stability of the linear regulator. Bias input and 4.2V linear regulator' output. This pin supplies the bias to some control circuits. The s 4.2V linear regulator converts the voltage on VIN to 4.2V to supply the bias when no external 5V power supply is connected with VCC. Connect a ceramic capacitor (1F typ.) between VCC and GND for noise decoupling and stability of the linear regulator. Power Switching Output. Connect this pin to the underside Exposed Pad. Output of error amplifier. Connect a series RC network from COMP to GND to compensate the regulation control loop. In some cases, an additional capacitor from COMP to GND is required for noise decoupling. Feedback Input. The IC senses feedback voltage via FB and regulate the voltage at 0.8V. Connecting FB with a resistor-divider from the output set the output voltage in the range from 0.8V to 90% VIN. Power and Signal Ground. Power Switching Output. LX is the Drain of the P-channel MOSFET to supply power to the output. The Exposed Pad provides current with lower impedance than Pin 5. Connect the pad to output LC filter via a top-layer thermal pad on PCBs. The PCB will be a heat sink of the IC.
2
EN
3
UGND
4
VCC
5 6
LX COMP
7 8 9 (Exposed Pad)
FB GND LX
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APW7080
Block Diagram
VIN
Current Sense Amplifier
VCC
VCC
4.2V Regulator and Power-On-Reset
Current Limit
POR 70%VREF Soft-Start and Fault Logic Inhibit Gate Control VREF 0.8V Error Amplifier UG Gate Driver
UVP Soft-Start
FB
Current Compartor
UGND
LX
VIN
COMP
ENOK 2.5V Slope Compensation Over Temperature Protection Oscillator 380kHz
5.5V
EN
0.8V
Enable
FB
VIN-to-UGND Linear Regulator
GND
Typical Application Circuit
1. 4.5~26V Single Power Input Step-down Converter (with Ceramic Input/Output Capacitors)
C1 10F
1
VIN 4 VCC UGND LX LX 3 9 5
4.5~26V
VIN
C2 1F
C3 1F R5 100k U1 APW7080
2 6 EN COMP GND
L1 4A
VOUT
D1 R1 1%
0.8V~90%VIN C4 /4A
22F
VIN
FB
7
R4 C6 C5
R2 1% C7 (Optional)
8
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APW7080
Typical Application Circuit (Cont.)
Recommended Feedback Compensation Network Components List:
VIN (V)
24 24 24 24 12 12 12 12 12 12 12 12 5 5 5 5 5 5
VOUT (V)
12 12 5 5 5 5 3.3 3.3 2 2 1.2 1.2 3.3 3.3 1.2 1.2 0.8 0.8
L1 (H)
15 15 10 10 10 10 10 10 4.7 4.7 3.3 3.3 3.3 3.3 2.2 2.2 2.2 2.2
C4 (F)
22 44 22 44 22 44 22 44 22 44 22 44 22 44 22 44 22 44
C4 ESR (m)
5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3
R1 (k)
140 140 63 63 63 63 46.9 46.9 30 30 7.5 7.5 46.9 46.9 7.5 7.5 0 0
R2 (k)
10 10 12 12 12 12 15 15 20 20 15 15 15 15 15 15 NC NC
C7 (pF)
22 22 33 33 68 68 82 82 56 56 150 150 68 68 270 270 NC NC
R4 (k)
62 120 24 51 24 51 15 33 10 20 6.2 12 15 33 5.6 12 2.7 6.2
C5 (pF)
820 820 1500 1500 820 820 1000 1000 2200 2200 3300 3300 560 560 1500 1500 2700 2700
C6 (pF)
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
2. Dual Power Inputs Step-down Converter (VIN=4.5~26V)
+5V
D2 Schottky Diode
4 VCC
C1 10F
1
VIN UGND LX LX 3 9 5
4.5~26V
VIN
C2 1F
C3 1F R5 100k U1 APW7080
2 6 EN COMP GND
L1 4A
VOUT
D1 R1 1%
0.8V~90%VIN C4 /4A
22F
VIN
FB
7
R4 C6 C5
R2 1% C7 (Optional)
8
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APW7080
Typical Application Circuit (Cont.)
3. 4.5~5.5V Single Power Input Step-down Converter
C1 10F
1
VIN 4 VCC UGND 3
4.5~5.5V
VIN
C2 1F L1 4A
C3 1F
LX
9 5
VOUT
D1 R1 1%
R5 100k
LX U1 APW7080 2 6 EN COMP GND FB
0.8V~90%VIN C4 /4A
22F
VIN
7
R4 C6 C5
R2 1% C7 (Optional)
4. +12V Single Power Input Step-down Converter (with Electrolytic Input/Output Capacitors)
8
VIN 4 VCC UGND LX LX
C1 2.2F
1
3 9 5
C8 +12V 470F
VIN
C2 1F
C3 1F R5 100k U1 APW7080
2 6 EN COMP GND
L1 10uH 4A
+3.3V/4A
D1 R1 46.9k 1% C4 470F (ESR=30m)
VOUT
VIN
R4 56k
FB
7
C6 22pF
C5 4700pF
R2 15k 1%
8
C7 33pF
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APW7080
Typical Application Circuit (Cont.)
5. -8V Inverting Converter with 4.5~5.5V Single Power Input
VIN
4.5~5.5V
C1 10F
3
1
R5 100k
2 EN
VIN UGND LX 4 LX VCC
C2 1F
9 5
C3 1F
U1 APW7080
FB 7
L1 6.8H 4A D1
6
COMP
R1 90k
PGND
C6 22pF
R4 39k C5 560pF
GND
R2 10k C7 27pF
AGND C4 22F
8
VOUT
-8V/4A
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APW7080
Function Description
Main Control Loop The APW7080 is a constant frequency current mode switching regulator. During normal operation, the internal P-channel power MOSFET is turned on each cycle when the oscillator sets an internal RS latch and would be turned off when an internal current comparator (ICMP) resets the latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the COMP pin, which is the output of the error amplifier (EAMP). An external resistive divider connected between VOUT and ground allows the EAMP to receive an output feedback voltage VFB at FB pin. When the load current increases, it causes a slight decrease in V FB relative to the 0.8V reference, which in turn causes the COMP voltage to increase until the average inductor current matches the new load current. VCC Power-On-Reset(POR) and EN Undervoltage Lockout The APW7080 keeps monitoring the voltage on VCC pin to prevent wrong logic operations which may occur when VCC voltage is not high enough for the internal control circuitry to operate. The VCC POR has a rising threshold of 3.9V (typical) with 0.15V of hysteresis. An external undervoltage lockout (UVLO) is sensed and programmed at the EN pin. The EN UVLO has a rising threshold of 2.5V with 0.2V of hysteresis. The EN UVLO should be programmed by connecting a resistive divider from VIN to EN to GND. After the VCC, EN, and VIN-to-UGND voltages exceed their respective voltage thresholds, the IC starts a start-up process and then ramps up the output voltage to the setting of output voltage. Connect a RC network from EN to GND to set a turn-on delay that can be used to sequence the output voltages of multiple devices. VCC 4.2V Linear Regulator VCC is the output terminal of the internal 4.2V linear regulator which is powered from VIN and provides power to the APW7080. The linear regulator is designed to be stable with a low-ESR ceramic output capacitor powers the internal control circuitry. Bypass VCC to GND with a ceramic capacitor of at least 0.22F. Place the capacitor physically close to the IC to provide good noise decoupling. The linear regulator is not intended for powering up any external loads. Do not connect any external loads to VCC. The linear regulator is also equipped with current-limit protection to protect itself during over-load or short-circuit conditions on VCC pin. VIN-to-UGND 5.5V Linear Regulator The built-in 5.5V linear regulator regulates a 5.5V voltage between VIN and UGND pins to supply bias and gate charge for the P-channel Power MOSFET gate driver. The linear regulator is designed to be stable with a low-ESR ceramic output capacitor of at least 0.22F. It is also equipped with current-limit function to protect itself during over-load or short-circuit conditions between VIN and UGND. The APW7080 shuts off the output of the converters when the output voltage of the linear regulator is below 3.5V (typical). The IC resumes working by initiating a new softstart process when the linear regulator' output voltage s is above the undervoltage lockout voltage threshold. Digital Soft-Start The APW7080 has a built-in digital soft-start to control the output voltage rise and limit the input current surge during start-up. During soft-start, an internal ramp, connected to the one of the positive inputs of the error amplifier, rises up from 0V to 1V to replace the reference voltage (0.8V) until the ramp voltage reaches the reference voltage. The device is designed with a preceding delay about 10.8ms (typical) before soft-start process. Output Undervoltage Protection In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. Before the current-limit circuit responds, the output voltage will fall out of the required regulation range. The undervoltage continually monitors the FB voltage after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the undervoltage threshold, the IC shuts down converter' output. s The undervoltage threshold is 70% of the nominal output
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APW7080
Function Description (Cont.)
Output Undervoltage Protection (Cont.) voltage. The undervoltage comparator has a built-in 2s noise filter to prevent the chips from wrong UVP shutdown caused by noise. The undervoltage protection works in a hiccup mode without latched shutdown. The IC will initiate a new soft-start process at the end of the preceeding delay. Over-Temperature Protection (OTP) The over-temperature circuit limits the junction temperature of the APW7080. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the power MOSFET, allowing the devices to cool. The thermal sensor allows the converter to start a start-up process and regulate the output voltage again after the junction temperature is cooled by 50 oC. The OTP is designed with a 50oC hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the IC. Enable/Shutdown Driving EN to ground places the APW7080 in shutdown. When in shutdown, the internal power MOSFET turns off, all internal circuitry shuts down and the quiescent supply current of VIN reduces to <1A (typical). Current-Limit Protection The APW7080 monitors the output current, flowing through the P-channel power MOSFET, and limits the current peak at current-limit level to prevent loads and the IC from damages during overload or short-circuit conditions. Frequency Foldback When the output is shortened to ground, the frequency of the oscillator will be reduced to about 80kHz. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. The oscillator' s frequency will gradually increase to its designed rate when the feedback voltage on FB again approaches 0.8V.
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APW7080
Application Information
Power Sequencing
VIN VIN CIN
The APW7080 can operate with sigle or dual power input(s). In dual-power applications, the voltage (VCC) applied at VCC pin must be lower than the voltage (VIN) on VIN pin. The reason is the internal parasitic diode from VCC to VIN will conduct due to the forward-voltage between VCC and VIN. Therefore, VIN must be provided before VCC. Setting Output Voltage The regulated output voltage is determined by:
IQ1
Q1
LX
L D1
IL ICOUT
IOUT VOUT ESR COUT
T=1/F OSC
R1 VOUT = 0.8 (1 + ) R2
(V)
VLX
DT
Suggested R2 is in the range from 1K to 20k. For portable applications, a 10k resistor is suggested for R2. To prevent stray pickup, locate resistors R1 and R2 close to APW7080. Input Capacitor Selection It is necessary to turn on the P-channel power MOSFET (Q1) each time when using small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current. Place the small ceramic capcaitors physically close to the VIN and between VIN and the anode of the Schottky diode (D1) The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current (IRMS) of the bulk input capacitor is calculated as the following equation:
I
IOUT
IL
IOUT
IQ1
I
ICOUT
VOUT
VOUT
Figure 1 Converter Waveforms
Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are the function of the switching frequency and the ripple current (I). The output ripple is the sum of the voltages, having phase shift, across the ESR and the ideal output capacitor. The peak-to-peak voltage of the ESR is calculated as the following equations:
D= I = VOUT + VD VIN + VD VOUT *(1 - D) FOSC *L
IRMS = IOUT D (1- D)
(A)
........... (1) ........... (2) (V) ........... (3)
where D is the duty cycle of the power MOSFET. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating.
VESR = I *ESR
where VD is the forward voltage drop of the diode. The peak-to-peak voltage of the ideal output capacitor is calculated as the following equation:
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APW7080
Application Information (Cont.)
Output Capacitor Selection (Cont.) I VCOUT = (V) 8 FOSC COUT and greater core losses. A reasonable starting point for ........... (4) setting ripple current is I 0.4 IOUT(MAX) . Remember, the maximum ripple current occurs at the maximum input voltage. The minimum inductance of the inductor is calculated by using the following equation:
VOUT *(VIN - VOUT) 1.2 380000 *L *VIN L VOUT *(VIN - VOUT ) 456000 *VIN (H)
For the applications using bulk capacitors, the V COUT is much smaller than the V ESR and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is shown below:
VOUT = I ESR (V)
........... (5) ........... (6)
For the applications using ceramic capacitors, the VESR is much smaller than the V COUT and can be ignored. Therefore, the AC peak-to-peak output voltage (VOUT ) is close to VCOUT . The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. An aluminum electrolytic capacitor' ESR value is related to the case size with lower s ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The equation (2) shows that the inductance value has a direct effect on ripple current. Accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple
where VIN = VIN(MAX)
Output Diode Selection The Schottky diode carries load current during the off-time. The average diode current is therefore dependent on the P-channel power MOSFET duty cycle. At high input voltages the diode conducts most of the time. As VIN approaches VOUT the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is short-circuited. Therefore, it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. Under normal load conditions, the average current conducted by the diode is:
ID = VIN - VOUT IOUT VIN + VD
The APW7080 is equipped with whole protections to reduce the power dissipation during short-circuit condition. Therefore, the maximum power dissipation of the diode is calculated from the maximum output current as:
PDIODE(MAX) = VD *ID(MAX)
where
IOUT = IOUT(MAX)
Remember to keep lead length short and observe proper grounding to avoid ringing and increased dissipation.
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APW7080
Layout Consideration
In high power switching regulator, a correct layout is important to ensure proper operation of the regulator. In general, interconnecting impedance should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 2 illustrates the layout, with bold lines indicating high current paths. Components along the bold lines should be placed close together. Below is a checklist for your layout:
D1 8 7 6 5
SOP-8P
5. Place the decoupling ceramic capacitor C1 near the VIN as close as possible. The bulk capacitors C8 are also placed near VIN. Use a wide power ground plane to connect the C1, C8, C4, and Schottky diode to provide a low impedance path between the components for large and high slew rate current.
1. Begin the layout by placing the power components first. Orient the power circuitry to achieve a clean power
C1
flow path. If possible, make all the connections on one side of the PCB with wide, copper filled areas. 2. In Figure 2, the loops with same color bold lines conduct high slew rate current. These interconnecting impedances should be minimized by using wide and short printed circuit traces. 3. Keep the sensitive small signal nodes (FB, COMP) away from switching nodes (LX or others) on the PCB. Therefore, place the feedback divider and the feedback compensation network close to the IC to avoid switching noise. Connect the ground of feedback divider directly to the GND pin of the IC using a dedicated ground trace. 4. The VCC decoupling capacitor should be right next to the VCC and GND pins. Capacitor C2 should be connected as close to the VIN and UGND pins as possible.
VLX
L1
VOUT C4 Load
VIN
1 2 3 4
GND GND
Figure 3 Recommended Layout Diagram
Thermal Consideration In Figure 4, the SOP-8P is a cost-effective package featuring a small size, like a standard SOP-8, and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VLX plane. The copper of the VLX plane on the Top layer conducts heat into the PCB and air. Please enlarge the area of VLX plan to reduces the case-to-ambient resistance (CA).
102 mil
+ VIN -
1
C2 1 VIN LX 5 3 UGND LX 9 4 VCC C3 2 D1 U1 APW7080 EN GND 8 FB 7 R2 R1
8
2
C1 C8 L1 + C4 Load VOUT 118 mil
3 4
SOP-8P
7 6 5
6 COMP C6 R4 C5
Die
C7
Ambient Air
(Optional) Feedback Divider
Exposed Pad
Top VLX plane
Compensation Network
PCB
Figure 2 Current Path Diagram
Figure 4
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APW7080
Package Information
SOP-8P
D SEE VIEW A D1 THERMAL PAD E2 E1
E
e
b
h X 45
c
0.25 GAUGE PLANE SEATING PLANE VIEW A
0
A2 A1
A
L
S Y M B O L A A1 A2 b c D D1 E E1 E2 e h L 0
SOP-8P MILLIMETERS MIN. MAX. 1.60 0.00 1.25 0.31 0.17 4.80 2.25 5.80 3.80 2.00 1.27 BSC 0.25 0.40 0o 0.50 1.27 8o 0.010 0.016 0o 0.51 0.25 5.00 3.50 6.20 4.00 3.00 0.15 0.000 0.049 0.012 0.007 0.189 0.098 0.228 0.150 0.079 0.050 BSC 0.020 0.050 8o 0.020 0.010 0.197 0.138 0.244 0.157 0.118 MIN. INCHES MAX. 0.063 0.006
Note : 1. Follow JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side.
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APW7080
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A
H
H A
T1
T1
C
d
D
W
E1
W
F 5.5O .05 0 K0
330.0O .00 50 MIN. 2 SOP- 8(P) P0 4.0O .10 0 P1 8.0O .10 0
12.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0O .05 0 D0 1.5+0.10 -0.00 D1 1.5 MIN.
20.2 MIN. 12.0O .30 1.75O .10 0 0 T A0 B0
0.6+0.00 0 0 0 -0.40 6.40O .20 5.20O .20 2.10O .20
(mm)
Devices Per Unit
Package Type SOP- 8P
Unit
Tape & Reel
Quantity
2500
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APW7080
Reflow Condition
TP Ramp-up TL Tsmax
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP
Temperature
tL
Tsmin ts Preheat Rampdown
25
t 25C to Peak
Time
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package. Measured on the body surface.
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APW7080
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5C 2.5 mm 225 +0/-5C Volume mm 350 225 +0/-5C 225 +0/-5C
3
Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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